The present invention relates to depositing copper onto a barrier or liner layer and especially concerned with providing a conformal adherent copper film.
The present invention finds particular applicability for VLSI and ULSI metal interconnects, studs, for CMOS gate stacks on semiconductor chips and for electrical interconnections in packaging and display sources.
The present invention is especially advantageous for depositing copper in high aspect ratio/trench structures ( greater than 3:1 depth/width).
Al(Cu) and its related alloys are a preferred alloy for forming interconnections on electronic devices such as integrated circuit chips. The amount of Cu in Al(Cu) is typically in the range from 0.3 to 4%.
Replacement of Al(Cu) by Cu and Cu alloys as a chip interconnection material results in advantages of performance. Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of Al(Cu), thus narrower lines can be used and higher wiring densities will be realized.
When fabricating high performance interconnect structures, the Cu conductive wiring material must be embedded into a dielectric material having a trench or via formed therein. The dielectric material may comprise an organic as well as an inorganic material, or combination thereof. Examples of such materials include polyimides, parylene polymers, polyarylene ether polymers, diamond-like carbon, materials comprising various amounts of carbon, silicon, oxygen and hydrogen, polysiloxanes, SiO2 and Si3N4. Such materials may be either dense or porous.
While Cu is the conductor of choice in such applications, it possesses an important undesirable property with respect to its interaction with the dielectric matrix. Copper generally diffuses through the dielectric material at the moderately elevated temperatures encountered during subsequent processing. This can have a number of deleterious consequences, including the possible short-circuiting of the wires or degradation of the performance of the MOS devices to which they are wired. To prevent these effects, it is therefore necessary to incorporate a diffusion barrier into the structure, isolating the Cu from the dielectric.
Among the materials suggested as barrier materials are tungsten (W) and its alloys, titanium, alloys of titanium, titanium nitride, tantalum, tantalum alloys, tantalum nitride and tantalum silicon nitride.
However, various coating methods which might be employed to form the copper wire, such as electroplating, evaporation, or electroless deposition from solution, result in unacceptably poor adhesion between the diffusion barrier and the copper wire. As a consequence, the structure thus formed lacks the ruggedness necessary to withstand subsequent processing steps, such as chemical-mechanical polishing (CMP) without incurring catastrophic structural failure.
As a consequence of the above adhesion problem, it has been found necessary in practice to deposit the Cu comprising the wire in two distinct steps. The first of these steps is to coat the diffusion barrier with a thin layer of Cu, typically a few hundred angstroms thick. In current practice, this layer, referred to as the seed layer, is deposited by sputter deposition as this has been the sole method discovered heretofore which provides good adhesion between the Cu and any of the materials used for the diffusion barrier layer. Once the seed layer is in place, the remainder of the Cu comprising the wire may be deposited by a number of methods, such as CVD or electroplating, as the adhesion between the bulk wire Cu and the seed layer Cu is not a problem. Two steps are required because it is impractical to fabricate the whole of the wire by sputter deposition, for a variety of reasons.
The necessity heretofore of using sputter deposition to form the seed layer leads to a second major problem. This is the problem of conformality. In practice today, and increasingly in the future, high performance wiring structures will contain high aspect ratio trenches in the dielectric. The aspect ratio is defined as the ratio of the depth of the trench to its width, and high aspect ratio refers to ratios of 3:1 or greater. Sputter deposition is inherently a poorly conformal process so that it is difficult to achieve adequate coverage of the seed layer on the side walls of the trench. This is undesirable as it will lead to a weakening of the structure. While sputter deposition processes may be xe2x80x9ctunedxe2x80x9d and modified by means well known to those skilled in the art so as to optimize the degree of conformality, this inherently involves complex and costly apparatus, and it is not apparent that it can be extended to meet foreseeable needs.
It would therefore be highly desirable to have a low cost, inherently conformal method to form the seed layer to replace sputter deposition.
A suggestion of a particular electroless copper deposition on a CVD tungsten diffusion barrier can be found in Mak et al, Electrochemical Society Proceedings, Vol. 93-20, 1993, Romankiw et al (Eds.), p. 233. Chemical vapor deposition (CVD) of the tungsten was achieved by the selective tungsten process using WF6 as tungsten source. In this process, W deposits selectively only on the bottom of exposed Si vias and trenches patterned in silicon dioxide, but not on silicon dioxide (SiO2). Subsequently, electroless copper is deposited selectively on the tungsten surfaces. FIG. 1 shows schematic representation of a Cu interconnection formed by the selective tungsten-electroless copper process. It is seen from FIG. 1 that Cu interconnection according to this process has diffusion barrier only on the bottom of interconnection. Thus, only diffusion of Cu into Si is blocked. However, Cu atoms may diffuse not only from the bottom of interconnections but also from the sides or the tops of the interconnections. Diffusion of Cu from the sides into SiO2 degrades the SiO2 insulator and results in defects. Thus, the product of this process is not satisfactory.
In another technique, silicon is implanted on the bottom of the SiO2 trench and then CVD W is selectively deposited on the implanted silicon. Electroless copper is selectively deposited on tungsten to produce the Cu interconnection (Angyal et al, Electrochemical Society Extended Abstracts, 93-1, 1993, p. 465). In this process, like in the previous one, Cu diffusion is blocked only at the bottom but not at the sides and Cu may easily diffuse into the SiO2 insulator. Thus, this process is not satisfactory either. FIG. 2 shows schematic representation of the process with Si seed layer implant.
Therefore, it would also be desirable to provide a process capable of fabricating completely encapsulated copper interconnections for integrated circuits.
The present invention makes it possible to conformally deposit the seed layer by a relatively low-cost and simple method.
It has been found according to the present invention that copper can be deposited from certain electroless deposition baths. Since electroless deposition does not involve the application of external electrical potentials, and does not possess any other characteristic which externally imposes a unique axis in space (such as the direction of propagation of the ion beam in sputtering process) it is inherently a conformal process and solves the problem of conformality. The present invention also solves the problem of adhesion which has heretofore prevented the use of electroless deposition for this purpose by employing compositions having certain characteristics. More particularly, the copper electroless plating baths employed pursuant to the present invention have a pH of at least 12.89 and a deposition rate of 50 nanometers/minute or less.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.